A power efficient EA modulator based on CBSC IIR filter in 0.18μm CMOS

In this paper a second-Order low distortion Sigma-Delta Modulator (SDM) with utilization of comparator-based switched-capacitor (CBSC)-based IIR filter, is explored. The advantages of this new structure are justified by the reductions of power and area. For this purpose IIR filter block can be made with single CBSC gain stage that has the same accuracy and performance of 2
^nd
-order filter with two Op-amps. This design is intended to minimize the power consumption, and maximize dynamic performance. As shown in the simulation result, for a 20-KHz signal bandwidth, the modulator achieves a dynamic range of 70.2 dB and a peak signal-to-noise and distortion ratio (SNDR) of 68 dB with an over-sampling ratio of 64. In addition it consumes 198 μW from a 1.8-V power supply at 2.56MS/s.