Real-time signal processing on low-cost-FPGAs using dynamic partial reconfiguration

The limited number of logic elements makes the implementation of signal processing chains on low-cost FPGAs a challenging task. In order to allow the implementation of complex designs on devices with limited resources, we propose the subpartitioning of a processing chain into several modules, which are loaded and executed in a round-robin fashion using dynamic partial reconfiguration (DPR) of FPGAs. The DPR architecture requires input data pre-buffering which introduces delay. These circumstances are first considered in a theoretical analysis and later applied to a broadcast receiver chain, where the benefits and drawbacks of the architecture are highlighted.