Hardware assisted thread assignment for RISC based MPSoCs in invasive computing

One of the major challenges of future many-core architectures is the efficient utilization of the abundance of computing power. Invasive computing provides a computing paradigm wherein applications can economically use the available compute resources. Applications can expand and shrink on demand depending on their thread level parallelism and resource availability. In this paper we present an analytical justification for performing a hardware-software co-optimization of the thread assignment in a resource aware programming environment. We propose a dedicated hardware block to support thread assignments as an architectural extension to standard MPSoC designs.