Nearly defect-free Ge gate-all-around FETs on Si substrates

The p-channel triangular Ge gate-all-around (GAA) FET with fin width (W
fin
) of 52nm and L
g
of 183nm has I
on
/I
off
=10
⁵
, SS= 130mV/dec, and I
on
=235 µA/µm at −1V. Performance can be further improved if superior gate stack than EOT=5.5 nm and D
it
=2×10
¹²
cm
⁻²
eV
⁻¹
is used. A novel process to etch away the high defect Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by GAA with larger effective width (W
eff
) than rectangular fin, and have low punch-through current through the Si substrate due to the oxide under the Ge channel and the valence band discontinuity at the Ge S/D and Si interface. By dislocation removal, the defect-free Ge channel can be formed on nothing.