Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction

We report a detailed study of the impact of systematic across-chip variation (ACV) on chip level power-performance. We propose a metric to capture impact of ACV on chip-level leakage quantitatively. Product power-performance can be optimized by minimizing systematic ACV. Thermally-driven ACV was identified as a major mechanism in 32nm SOI technology. An optimized thermal anneal process was used to suppress ACV significantly, leading to a dramatic benefit in leakage power-performance trade-off.