Worst-case test vectors of sequential ASiCS exposed to total dose

We introduce a novel methodology for identifying worst-case test vectors for sequential circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use of sequence of test vectors. Those test vectors we generated using cell-level fault models for failures induced by total dose. In this paper we focused on three types of failures: logic, leakage current, and delay failures. A novel cell-level fault model for delay failures induced by total dose is introduced in this paper. This methodology was validated using SPICE simulation as well as experimental results.