The impact of channel-width on threshold voltage for short channel devices

Technology advances has enabled reduction in transistor dimensions to almost nm scale dimensions as low as 25 nm. CMOS circuits designed for deep submicron technology have imposed new design challenges called as submicron or second order short channel effects (SCE). These SCE contribute to maximum static power dissipation and are closely related to the aspect ratio of the device. In this paper, we present behavior of a low power multi supply voltage (multi-V
DD
) interface circuit with respect to variation in aspect ratio of the sleep transistor. The simulation results show variation of threshold voltage for given technology with respect to the variation in channel width in contrast to previous device theory which says threshold voltage is process dependent. We have tried to optimize the level shifter circuit for high performance and low power by varying channel width. The circuit performance can be improved by increasing channel width of transistors in critical path and decreasing channel width for sleep transistor resulting in high threshold voltage. This reduces sub threshold, short circuit and leakage currents. Simulations have been carried out using Cadence Virtuoso Spectre simulator with 0.18µm technology.