Versatile FPGA Architecture for Skein Hashing Algorithm

This paper focuses on the design and analysis of a versatile Field Programmable Gate Array (FPGA) hardware for the Skein hashing algorithm. A single design capable of processing individual messages sequentially, multiple messages using pipelined architecture, or executing Skein's tree hashing mode using the same pipelined architecture was developed for the Skein-256 version of the algorithm. Emphasis was placed on efficient use of FPGA resources and detailed performance analysis of pipelined tree hashing. The design is compared with current sequential and tree hashing FPGA implementations. The post place-and-route results show that our design achieves a maximum throughput of 1.4Gbps in sequential mode, 6.6Gbps in multiple message mode, and 6.6Gbps in tree hashing mode on a Virtex-5 FPGA and 1.5Gbps, 7.7Gbps, and 7.7Gbps on a Virtex-6 respectively.