A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM

This paper presents a low-power small-area open loop digital DLL. The DLL has open loop single replica block with duty cycle corrector (DCC), clock divider, pulse generator, 10-bit counter, and delay line. The DLL used for 2.2Gb/s/pin 2Gb DDR3 SDRAM is fabricated using 44nm DRAM Process. Experimental results show 1.1GHz operation frequency at 1.5V, and the measured total power and area savings in comparison with the conventional closed-loop operation is about 93.5% and 90.7% respectively.