A 2.1-GHz PLL with −80dBc/−74dBc reference spur based on aperture-phase detector and phase-to-analog converter

This paper presents a 2.1-GHz PLL with low power consumption, low in-band phase noise and low reference spur. A new aperture-phase detector (APD) compares the phases between reference and VCO output in a time window, which eliminates the power and noise contributions from the divider. At the end of phase detection, a phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error and then controls the current amplitude of the following charge pump (CP) circuit. When transferred to PLL output, CP noise is not multiplied by N² compared with a conventional PLL, which leads to the PLL with lower in-band phase noise. In the proposed CP, the charging and discharging currents have equal pulse width and equal amplitude close to zero when PLL is locked, resulting in a low reference spur and super-low power consumption of CP. The proposed PLL is implemented in TSMC 0.13μm CMOS process, which consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm excluding PAD. Measurement results indicate that the PLL achieves a reference spur level of −80dBc/−74dBc, and an in-band phase noise of −103 dBc/Hz at 100 kHz offset.