A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology

This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalizer front-end with digital adaptation, and a sub-rate clock and data recovery circuit using majority voting phase detection. The transceiver delivers 40-Gb/s 2
$^{7}-$
1 PRBS data across a Rogers channel of 20 cm (19-dB loss at 20 GHz) with BER
$ < \hbox{10}^{-12}$
while consuming a total power of 655 mW.