Design of the Multi-encrypted Circuit Based on FPGA

In this paper, a FPGA-based design method of the multi-encrypted and layer-granted circuit has been proposed, overcoming program fleeting and worse reliability based on MCU. Three-encryption circuit with four bits password of each stage was described in VHDL language on Quartus II. And the method was also proposed of expanding number of password bits. The circuit has been realized on the EP1C3T144C8 chip of Altera's FPGA which is low cost. The system could be upgraded and improved effectively by using the in-system programmable (ISP) speciality of FPGA. The experiment result shows that the circuit has the functions of multi-encrypted, arbitrary bits password and password error alarm. And the safe reliability of the system can be effectively improved.