Low-power energy-based CMOS digital detector for neural recording arrays

Recent research works in wireless neural recording systems by microelectrode arrays favor spikes extraction to limit the required bandwidth. While simple thresholding locates spikes, using an adequate pre-processor before thresholding can improve the performances of detection. We present in this paper low-power implementations of three interesting energy-based preprocessors (Abs, TEO, and Smoothed-TEO). The proposed novel spike detection module allows a trade-off between silicon area and power consumption of the system. Performances have been evaluated with recorded neural signals from monkeys to determine the optimal trade-off. The post-routed power estimation showed that the implementation of the optimal detection pre-processor tested in this work, the Smoothed-TEO, achieves 961 nW per channel and occupies a silicon area of 0.008 mm
²
per channel.