Low power efficient built in self test

This paper proposes a low power efficient Built in Self Test (BIST) with Test Pattern Generation (TPG) technique, which reduces power dissipation during testing. In general, the correlations between the consecutive test patterns are higher during normal mode than during testing mode. The proposed approach uses the concept of reducing the transitions in the test patterns generated by conventional Linear Feedback Shift Register (LFSR) . The transitions are reduced by increasing the correlation between the successive bits in the test pattern, which is done with the help of modified LFSR. This approach eliminates the need for an external tester. The simulation result shows that the power dissipated during testing is reduced in modified LFSR than in conventional LFSR.