On the Feasibility of Built-In Self Repair for Logic Circuits

According to recent investigations on fault mechanisms in nano-scale integrated circuits, they suffer from wear-out effects that limit their life time seriously. For applications that combine a long life time and safety-critical functionality, means of fault compensation, de-stressing and eventual self repair are therefore becoming a must. This paper presents a circuit architecture that combines capabilities of self repair and de-stressing for logic circuits. Circuits that administrate repair functions are introduced. The necessary overhead for redundancy as well as for circuit re-organization is shown, depending on the granularity of repair. Finally limitations as well as single points of failure are discussed.