Low-Power 10-Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18- $\mu\hbox{m}$ CMOS Technology

This brief presents a 10-Gb/s transmitter using a low-power one-stage 8:1 multiplexer. In the proposed transmitter, a differential current-steering output driver with a multiphase multiplexer architecture is used to alleviate speed limitations of the DRAM process. The current-steering output driver reduces the required output swing and increases the bandwidth of the multiplexer. The proposed multiplexer accomplishes not only high-speed operation but also low power dissipation by using a pseudo-nMOS configuration with one-stacked switches and reducing the short-circuit current of the gate driver in the multiplexer. The prototype of the transmitter using a 0.18- μm CMOS technology achieves the power efficiency of 5.69 mW/Gb/s at the data rate of 10 Gb/s.