Design of a temporal learning chip for signal generation and classification

A recurrent neural network with temporal learning is designed in CMOS Technology. The developed learning rule extends the temporal learning to realize a forward instantaneous update scheme, suitable for analog hardware implementation. We have designed 4-neuron and 6-neuron prototypes. PSPICE simulations have been used to verify the design. Moreover, a 2-dimensional scalable array configuration with learning is constructed for simple scalable VLSI Architecture. The focus is on learning and generating periodic signals, as well as learning and classifying temporal signals. In this work, only the design and simulations are reported.