A new first-order switched-current sigma-delta modulator with improved linearity

This paper describes a 12-bit, 3.4 kHz bandwidth, switched-current sigma-delta modulator for voiceband applications. This is based on a classical first order architecture employing a novel technique of error reduction on the current memory cells that leads to a significant improvement of the overall circuit linearity. From the viewpoints of power dissipation and silicon area such an error reduction technique offers a competitive alternative to currently available high-linearity switched-current memory cells. The circuit operates with a clock frequency of up to 2 MHz, including sampling, correction error and hold phases. The oversampling ratio is 128 for the nominal 300-3,400 Hz bandwidth. The modulator has been fabricated by using a single-poly double-metal standard digital 0.8 /spl mu/m CMOS process with an active area of merely 0.21 mm/sup 2/. The circuit dissipates 7 mW at 2 MHz clock frequency while operating from a single 5 V power supply.