Novel CMOS CCCII structure based on multiple differential pairs

There are two major methods implementing a second generation current controlled conveyor (CCCII) based on CMOS technology. The first is based on a translinear loop and the second is based on balanced differential pairs. Though the balanced differential-pair performs better in most perspective, it is suffered from higher intrinsic transresistance in a ceteris paribus comparison. In this work, the gain of a PMOS differential-pair is utilized as a divider to the intrinsic transresistance at port X (R
_x
). Though the total number of MOSFETs is slightly increased, the obtained transresistance is significantly reduced by the gain of a preamplifier differential-pair module. To test the design efficiency, HSPICE simulations based on the IBM 90nm RF CMOS parameters extracted by the MOSIS are conducted under ±0.5V supply voltage. In comparison to the simple balanced differential-pair structure, the proposed modified version provides significant reduction in R
_x
and still maintains good behavior of voltage and current gains.