Design and implementation of a clock recovery circuit for fast Ethernet applications

A circuit architechure to realize clock recovery for fast Ethernet applications is presented, whick includies system architecture, modified Mueller Muller algorithm for 100BASE-TX, phase detector for 100BASE-TX and multiple output charge pump PLL. The clock recovery circuit is verified by TSMC 0. 35μm 1P5M CMOS process. The results show that this clock recovery circuit exactly extracts the timing information. It has advantages over others for simple and easy implementation.