Analysis of low power open core protocol bridge interface using VHDL

System on Chip (SoC) design is becoming challenging due to its complexity and the necessity of Intellectual Properties (IP) reuse to shorten the design time. An efficient bus protocol for the core communication between IP block is OCP. Open Core Protocol (OCP) defines the only non-proprietary, openly licensed, core centric protocol with high-performance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs and promote IP core reusability for SOC designs. Bus Bridge interconnects other bus standard to OCP. I2C is a simple bi-directional two wire bus for efficient inter IC control. This paper focus on the design and implementation of Bus Bridge using OCP master and I2C slave protocol. The power reduction using Multi voltage design is the important feature of the paper. The developed FSM's for OCP and I2C were implemented in VHDL and the Synthesis is done using Xilinx ISE 10.1 and Synopsys ASIC synthesis tool design compiler.