Design of an eFuse OTP memory of 8 bits based on a 0.35µm BCD process

In this paper, we design an 8-bit eFuse OTP (one-time programmable) memory based on a BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. The layout size of the designed 8-bit eFuse OTP memory IP is 142μm × 380.725μm.