An all-digital PLL synthesized from a digital standard cell library in 65nm CMOS

This paper presents an all-digital PLL (ADPLL) in which all functional blocks have been synthesized from standard digital cells and automatically placed and routed (P&R). A calibration scheme is proposed to account for the systematic mismatch resulting from P&R. The ADPLL is fabricated in 65nm CMOS and occupies 0.042mm
²
. The period jitter is 3.2ps
_rms
(36ps
_pp
) at 2.5GHz, and the power consumption is 9.1mW to 14.6mW over a 1.5 to 2.7GHz frequency range.