Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs

We discuss dynamic stability for single-port SRAM that manifests itself in the difference between minimum operating voltage (Vmin) for longer and shorter word-line (WL) pulse width (T
_wl
). The most probable failure points (MPFPs) that determine Vmin for various T
_wl
are investigated. Regarding dual-port SRAM, we identify the MPFP for the worst Vmin degraded by WL pulse skew between ports in asynchronous operation. The validity of our simulation results are verified through comparison with measured data for SRAM modules in 28 nm generation.