FPGA implementation of an associative content addressable memory

The content addressable memory (CAM) is allowed to search a data without knowing its address as to common memories. In addition, it allowed associating the content of the location or neighboring locations where the data word was identified. A problem that occurs to this type of memory is implementation complexity. A possible solution is to use a hardware implemented Hopfield neural network. This paper presents our own approach for FPGA hardware implementation of the CAM memory. Will be presented design methods and implementation to FPGA circuit structures, the performance of our solution and experimental results.