A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs

Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.