Abstract:
We present architectural and circuit design details of a single-bit continuous-time ΔΣ modulator in 0.13 μm CMOS sampling at 1 GS/s. The “assisted opamp technique” is use...Show MoreMetadata
Abstract:
We present architectural and circuit design details of a single-bit continuous-time ΔΣ modulator in 0.13 μm CMOS sampling at 1 GS/s. The “assisted opamp technique” is used to obtain high linearity with low power consumption. Analysis of the effects of timing-skew between the feedback and assistant DACs is given. The converter achieves a dynamic range of 67 dB in 15.6 MHz bandwidth and consumes 4 mW. The figure of merit (FOM) of the modulator is 93 fJ/level.
Published in: 2011 Proceedings of the ESSCIRC (ESSCIRC)
Date of Conference: 12-16 September 2011
Date Added to IEEE Xplore: 13 October 2011
ISBN Information:
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