A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range

We present architectural and circuit design details of a single-bit continuous-time ΔΣ modulator in 0.13 μm CMOS sampling at 1 GS/s. The “assisted opamp technique” is used to obtain high linearity with low power consumption. Analysis of the effects of timing-skew between the feedback and assistant DACs is given. The converter achieves a dynamic range of 67 dB in 15.6 MHz bandwidth and consumes 4 mW. The figure of merit (FOM) of the modulator is 93 fJ/level.