A stimulator ASIC with capability of neural recording during inter-phase delay

This paper presents a single chip solution for a combined stimulation and recording system for functional electrical stimulation applications. The on-chip recording amplifier blanks large stimulation artifacts occurring in the cathodic (i.e., stimulation) and anodic (i.e., recuperation) phases of a stimulation pulse. By making the stimulator output stage float and recording during the delay between cathodic and anodic impulses, the recording start time can be greatly advanced from the end of a complete stimulation cycle to the end of the cathodic phase. The ASIC was fabricated in a 0.6 μm HV CMOS technology, occupies a core area of 5.3 mm
²
and operates from a single 18 V power supply. It has 5 I/O pads for power and data communication and another 5 I/O pads for connecting to the electrodes. The operation of the ASIC has been verified both in-vitro and in-vivo.