On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure

Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 65 nm CMOS process. The proposed method achieves 46.9% and 57.9% noise reduction for wake-up noise and 130 MHz periodic supply noise, respectively. The proposed method also realizes without discharging time before noise cancelling, and shows a 8.4× boost of effective capacitance value with 2.1% chip area overhead. To apply the proposed switched parasitic capacitors of sleep blocks for reducing resonant supply noise, we can save chip area for noise reduction more effectively.