The VLSI design of a digital fuzzification circuit for a 4 input CMOS fuzzy processor running at a rate of 320 ns

The paper first summarizes the architecture of a VLSI fuzzy processor that can be fabricated in 0.7 /spl mu/m digital CMOS technology. This processor is able to process a four 7-bit input data set every 320 ns. This rate increases up to 100 ns if only two inputs are processed. The innovative feature of this design is the independence of the processing rate from the fuzzy system. The fuzzy chip architecture is pipelined and each step takes 20 ns. We describe in this paper the fuzzification process: in our solution the membership functions (MFs) have a triangular shape, therefore there is a memory where the related points necessary to define the shape are stored. In one pipeline step the MF shape is generated and in the following step the grade of truth /spl alpha/ is computed. In this paper we describe in details the circuit.