Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer

In a conventional analog adaptive forward equalizer (FE), parasitic capacitance introduces an undesired RC pole at the output node of the equalizer. At high data rates, this pole can introduce intersymbol interference (ISI) that degrades performance. This paper considers the effect of the parasitic pole and presents two approaches to deal with the parasitic pole. The first approach uses an extra tap in the FE; the second uses chopping. Also, the filtered-x LMS (FX-LMS) algorithm is used to allow the equalizer to adapt and correct for the parasitic pole. Implementations of the FX-LMS algorithm and the chopper technique are presented. The conventional and new architectures and various adaptation algorithms are compared via simulation.