FPGA implementation of joint CFO and IQ-imbalance compensator for narrow-band wireless system

In direct conversion receiver, I/Q imbalance is caused by non orthogonality between in-phase component and quadrature-phase component caused by imperfections of quadrature demodulator. In addition, carrier frequency offset (CFO) occurs as well. In this paper, we present a register transfer level (RTL) design of joint CFO and I/Q imbalance compensator. First, we verify the efficiency of compensation algorithm with computer simulation, and then we show a bit error rate (BER) characteristic. After that, we made an RTL design to compensate CFO and I/Q imbalance.We also measure the efficiency of system in this step by looking at constellation of received signal. Finally, we implement the RTL design of compensation system in a field programmable gate array (FPGA). We show the effect of compensation system by simulation on RTL and verification on FPGA.