A novel dual edge triggered near-threshold state retentive latch design

This paper proposes a new dual edge triggered near threshold state-retentive latch for low-power applications. The proposed circuit uses the idea of power gating during the sleep or idle mode thereby avoiding leakage but still retaining its state. It uses a dual edge triggered pulse which is a pulse trigger at both the rising and falling edges of the clock. The circuit used low Vth Devices only and hence can operate at a Vdd as low as 0.5 V. The circuit was simulated using HSPICE at 45nm technology. When compared with respect to power delay product, at an operating voltage of 0.9V the proposed circuit has PDP 87.8% less than DET_SRSFF, 71.6%less than IDDA- LCFF. When the proposed circuit operates at 0.5 V and the reference circuits operated at 0.9 V, PDP of the proposed latch is: 78.26% less than DET_SRSFF and 50% less than that of IDDA-LCCF. In case of setup time, the proposed latch has that 68% less than the IDDA-LCCF and 80% less than the DET_SRSFF. Also, when operated at Vdd =0.5 V, the proposed circuit has 29% less than IDDA-LCCF and 55.4% less than the DET_SRSFF when they were operated at Vdd=0.9 V.