Multi-merged-switched redundant capacitive DACs for 2b/cycle SAR ADC

This paper introduces a novel switch approach for redundant capacitive DACs of a 2b-per-cycle SAR ADC. By using the proposed multi-merged switching algorithm, the conventional trial-and-error search procedure is prevented, which leads to significant switching energy and DAC settling time reductions. The conversion power and speed analysis are presented, which is also verified in behavior simulations of a 6-bit 2b/cycle SAR ADC. The simulation results show that the proposed method can achieve about 37% power saving as compared to the conventional one.