A 3.1–10.6 GHz ultra-wide band CMOS low noise amplifier with band rejection

This paper presents an ultra wideband (UWB) low noise amplifier (LNA) with band rejection which is implemented with TSMC 0.18-µm CMOS process. In the proposed chip, a shunt peaking technique is used to have a considerably gain flatness; and that a notch filter with negative resistance is adopted with band rejection between 4.7–6.3 GHz. Besides, the power consumption is reduced using the current reused method and source inductor. The simulation results of the proposed UWB LNA with band rejection show that the input return loss (S11), output return loss (S22), gain (S21) and noise figure (NF) are −14.35 dB, −10.05 dB, 14.85 dB and 3.77 dB, respectively, at 3.1 GHz; and that the S11, S22, S21 and NF are −22.92 dB, −10.01 dB, 14.26 dB and 3.87 dB, respectively, at 10.6 GHz. Notify that the power consumption is about 20.4 mW and the maximum gain rejection is roughly 35.7 dB within 4.7–6.3 GHz.