Compressed sensing based analytical modeling for Through-Silicon-Via pairs

Through-Silicon-Vias (TSVs) are the critical enabling technique for three-dimensional integrated circuits (3D ICs). While there are a few existing works in literature to model the electrical performance of TSVs, they are either for fixed geometry or in lack of accuracy. In this paper, we use compressed sensing technique to model the electrical performance of TSV pairs. Experimental results indicate that with an exceptionally small number of samples, our model has a maximum relative error of 3.94% compared with full-wave simulations over a wide range of geometry parameters and frequencies.