Performance-power tradeoffs of 8T FinFET SRAM cells

We present eight eight-transistor (8T) FinFET SRAM cells which differ in back-gate connections and swing of the Read-line input. These schemes are evaluated in terms of leakage current, delay, read and write energy dissipation, and static noise margin (SNM) for 16 bits by 16 words (16×16) and 32 bits by 1024 words (32×1024) SRAM arrays. Performance is compared between the 8T schemes and two well-performing six-transistor (6T) SRAM cells. Overall, the 8T-SRAM schemes perform better than the 6T schemes primarily because leakage current is reduced by low-power schemes that reverse-bias the back-gates of the cross-coupled inverters without an adverse impact on the read speed. This is especially true for larger SRAM arrays, e.g. 32×1024. For a 32×1024 SRAM array, the best performing 8T scheme, Low-Power Inverters (LP_INV), has an energy-delay product that is 87.3% less than the best-performing 6T scheme, Low-Power (minimum-sized) (LP6).