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Assessment and comparison of IC Layout Designs | IEEE Conference Publication | IEEE Xplore

Assessment and comparison of IC Layout Designs


Abstract:

ICs have become pervasive in practically all electronic applications and products. Continuous innovation and tailoring design techniques have spawned several IC designs c...Show More

Abstract:

ICs have become pervasive in practically all electronic applications and products. Continuous innovation and tailoring design techniques have spawned several IC designs catering to distinct uses. The paper highlights the matters of comparison of Integrated Circuit (IC) Layout Designs (LDs) using industry standard and custom Electronic Computer Aided Design (ECAD) tools and reports their performance viz -aviz some key attributes for IC layout design comparison. The features of the tools for Cadence-Virtuoso; Mentor-Caliber;Synopsis-Hercules; Tanner LEdit, and the two customized tools Softjin-NxCompare and ICLDDTvl are described along with detailed IC layout comparison example performance runs with Softjin tools. An assessment on catching potential copying or infringements between given IC designs was checked through appropriate GDSII files of the design. From the analysis of the various features and results reported in this paper , it is concluded that the standard IC Design tools lack in their efficiency in terms of layout geometric comparisons and the customized tools demonstrate superior performances proving their immense value for robust comparison of any given Integrated Circuit Layout Design geometric patterns i.e .gds files . The later tools by virtue of their superior functional attributes and analysis abilities could cater to determination of distinctiveness of IC LD patterns as well as absence or extent of copying inherent between two IC LD files ( a new LD filed and a gold reference LD file in data base) for Intellectual Property (IP) determinations. The later tools could also aid the IC Designer in the enhancing the innovation process and tagging the third party IPs mapped in to the design.
Date of Conference: 21-22 July 2011
Date Added to IEEE Xplore: 22 September 2011
ISBN Information:
Conference Location: Thuckalay, India

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