On a gate sizing of multiple-paths circuit for optimizing power-delay

Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. In the previous work [1], the method of optimizing power-delay efficiency in a logical path showed about 40% greater efficiency in power dissipation than the existing technique [2]. However, our previous technique [1] is constrained for a single logical path. In this paper, we extend it for a multiple logical paths and thus, determine the gate size according to the formula derived in this paper.