An area reduced, speed optimized implementation of viterbi decoder

A fast implementation of the Viterbi decoder is discussed in this paper. It is shown that the proposed design is area efficient, reduces memory requirements and has a larger throughput then parallel Viterbi implementations. Techniques used to achieve these goals are retiming, pipelining and parallel to serial conversion which are implemented at the gate level. VLSI designs of constituent blocks of the decoder are shown and thorough analysis of the critical path delay of each decoder segment is deliberated which illustrates that the resulting design imposes minimum penalties in terms of clock speed and circuit area.