Novel high efficiency multilevel DC-DC boost converter topologies and modulation strategies

In this paper new topologies and interleaving modulation concepts for multilevel DC-DC boost converter enabling a significantly less loss and a reduced chip size of the power semiconductors are proposed. Moreover, a new soft switching concept is presented. The achievable efficiency, chip area and boost inductance reduction are compared with existing solutions for V
_In
= 800V, V
_Out
= 3kV and P
_Out
= 150 kW. A 30% loss reduction and a chip area decrease by 50% is achieved.