ATSC-M/H hardware multiplexer using simple bus arbitration and rate adaptation

In this paper, we present an advanced television systems committee-mobile/handheld (ATSC-M/H) hardware multiplexer for mobile broadcasting services. The entire system consists of a processor, a pre-processor engine, memory, and external interface blocks. Specifically, we address the key design issues such as how to reduce memory access time for handling large amounts of data, how to recover from inaccurate data rates of the legacy ATSC packets, and how to synchronize various function blocks with different data rates. The proposed multiplexer simplifies interface circuits between functional blocks and reduces memory access time through simple bus arbitration. It also provides robustness against inaccurate data rates of the DTV service packets by using a rate adaptation scheme. The preprocessor engine is implemented in an FPGA device and operates at a clock speed of 40 MHz. The proposed system is fully compliant with the ATSC-M/H standard.