Modeling of parasitic phenomena in trench technology

The paper describes SPICE modeling of a substrate PNP transistor in a bipolar technology that makes use of trench isolation. This parasitic transistor gives rise to a significant increase of the collector current in measured output characteristics at about Vce=−2V. Measured Gummel plots also showed non-standard behavior at Vce > −2V. A physical basis of the electrical behavior was determined and captured by a SPICE macro model.