Application of smart pixels to digital image halftoning

An innovative circuit for digital image halftoning applications has been implemented in several different hybrid fabrication processes. The circuits have been demonstrated to be compatible with several approaches to smart pixels and offer a wide range of options for realizing optical inputs and outputs. The 0.8 micron n-well CMOS process at MOSIS has been used in conjunction with SEED technology to implement a digital image halftoning algorithm that offers the potential for higher quality binary images. Similar algorithms have also been implemented using combined CMOS and liquid crystal on silicon processes as well as the Vitesse H-GaAs III foundry process.