Optimization of spanning tree carry lookahead adders

This paper examines the optimization of the 64-bit spanning tree carry lookahead adder by sizing the transistors in the different Manchester carry chain blocks and by adjusting the block widths within the carry tree to reduce the critical delay paths of the carry signals. Previous spanning tree designs are re-simulated using HSPICE, with parameters for a 0.35 /spl mu/m CMOS process, to compare against the circuits designed for this paper. After analyzing many different configurations using the 16-bit carry select boundary, two circuits employing an 8-bit carry select boundary are designed and simulated.