A RTL partitioning method with a fast min-cut improvement algorithm

A design flow with register transfer level (RTL) partitioning and an RTL partitioning algorithm for efficient logic synthesis and layout are described in this paper. By changing the parameter of the partitioning optimization dynamically, the algorithm improves the interconnection cost in a short CPU time. Experimental results on large circuits show that the algorithm partitioned circuits with a large number of RTL components in 1/10 to 1/100 of conventional partitioning times.