Single event effects on CVSL and CMOS exclusive-OR (EX-OR) circuits

Single event transient (SET) effects on cascade voltage switch logic (CVSL) exclusive-OR (EX-OR) circuits have been investigated using SPICE. CVSL and CMOS chain circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS process. Both circuits have been confirmed to function correctly by the fabricated chip measurements. SET simulation results have confirmed that the CVSL circuits have increased tolerance to SET. SET tolerance for the CVSL EX-OR is compared to that for the conventional CMOS EX-OR, showing that the CVSL is a candidate for a SET tolerant spaceborne logic circuit.