A comparator-based cyclic analog-to-digital converter with boosted preset voltage

In this paper, we describe a cyclic ADC to adopt the comparator-based switched-capacitor (CBSC) technique, for the first time, so as to compensate for the technology scaling and reduce power consumption by eliminating the need for high gain opamps. A boosted preset voltage is also introduced to improve the conversion rate without consuming more power. The ADC operates at 2.5MS/s, and near the Nyquist-rate, a prototype has a signal-to-noise and distortion ratio (SNDR) of 55.99 dB and a spurious-free dynamic-range (SFDR) of 66.85 dB. The chip was fabricated in 0.18μm CMOS and it has an active area of 0.146mm
²
and consumes 0.74mW from a 1.8V supply.