Characterization and failure analysis of Sub-10 nm diameter, gate-all-around nanowire field-effect transistors subject to electrostatic discharge (ESD)

Electrostatic discharge (ESD) robustness of the Sub-10 nm diameter gate-all-around nanowire field-effect transistor (NW FET) was characterized and compared with sub 65nm MOS devices and FinFETs. Failure mechanisms of NW FETs subject to ESD stresses are investigated by DC current-voltage measurements carried out before and after stressing the devices with ESD equivalent pulses generated from the transmission line pulsing (TLP) tester.