A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation

A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90 nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8 MHz signal bandwidth and consumes 4.3 mW.